M.S. in Computer Engineering at University of California, Davis. Area of research was computer vision using GPU / parallel computing.
B.S. in Computer Engineering at University of California, Davis. With an emphasis on embedded systems.
Interested in embedded systems in the consumer and automotive spaces. Passionate about graphics devices (GPU's) and their applications; especially in novel ways of integrating this technology in new environments to improve safety and performance of vehicles and other machines.
Especially focused on techniques which fully utilize the limited hardware resources provided on a platform in order to achieve the desired performance.
Specialties: Computer vision, parallel computing, computer and graphics architecture, microcontrollers, and DSP's.
My resume is available below:
Age Genie is an age recognizer application.
Date completed: March, 2012.
Approved for release: April 3rd, 2012.
An iPhone application exploiting the concept of Presbycusis (hearing loss with age). The app plays a series of sounds with different frequencies and asks the user to mark the ones they heard. Using this information and an estimate of hearing loss with age, it determines the user's possible age range.
Advanced Technology Engineer at the BMW Technology Office USA in Mountain View, CA.
Dates: October 2009 to February 2012.
Worked on introducing the first rich-content smartphone integration into BMW Group's infotainment system. Introduced BMW Apps and MINI Connected. Worked on the application connectivity platform team which created the iPhone applications Pandora and MOG, and integrated Apple's iPodOut mode.
Embedded Multimedia Engineering Intern at NVIDIA Corp. in Santa Clara CA.
Dates: May 2009 to October 2009.
Designed and implemented a framework for evaluating the accuracy, performance, and scalability of driver-assistance algorithms for automotive applications. Created an optimal OpenGL and CUDA image processing pipeline in order to yield optimal performance. Framework could be used on variety of different hardware configurations to test the scalability of an image processing system.
Vladimir Glavtchev, “EU Speed-limit Sign Detection Using a Graphics Processing Unit,” Masters Thesis, Electrical and Computer Engineering, University of California Davis, December 2009. [PDF] [BibTeX]
Abstract In this study we test the idea of using a graphics processing unit (GPU) as an em- bedded co-processor for real-time speed-limit sign detection. We implement a sys- tem that operates in real-time within the computational limits of contemporary em- bedded general-purpose processors. The input to the system is a set of grayscale videos recorded from a camera mounted in a vehicle. We implement a new tech- nique to realize the radial symmetry transform e±ciently using rendering primi- tives accelerated by graphics hardware to detect the location of speed-limit sign candidates. The system reaches up to 88% detection rate and runs at 33 frames per second on video sequences with VGA (640x480) resolution on an embedded system with an Intel Atom 230 @ 1.67 GHz and a Nvidia GeForce 9200M GS.
Below is a list of my research publications (in reverse chronological order):
Vladimir Glavtchev, Pınar Muyan-Özçelik, Jeffery M. Ota, and John D. Owens, “Feature-Based Speed Limit Sign Detection Using a Graphics Processing Unit." In Proc. of IEEE Intelligent Vehicles Symposium, pages 195-200, June 2011.
Abstract In this study we test the idea of using a graphics processing unit (GPU) as an embedded co-processor for realtime detection of European Union (EU) speed-limit signs. The input to the system is a set of grayscale videos recorded from a forward-facing camera mounted in a vehicle. We introduce a new technique for implementing the radial symmetry detector (RSD) efficiently using the native rendering capabilities of a GPU. The technique maps the algorithms to the hardware such that the detection of speed-limit sign candidates is significantly accelerated. The system reaches up to 88% detection rate and runs at 33 frames per second on video sequences with VGA (640x480) resolution on an embedded system with an Intel Atom 230 @ 1.67 GHz CPU and a NVIDIA GeForce 9400M GS GPU.
Pınar Muyan-Özçelik, Vladimir Glavtchev, Jeffrey M. Ota, and John D. Owens, “Real-Time Speed-Limit-Sign Recognition on an Embedded System Using a GPU." In Wen-mei W. Hwu, editor, GPU Computing Gems, volume 1, chapater 32, Morgan Kaufmann, February 2011.
Abstract We address the challenging problem of detecting and classifying speed-limit signs in a real-time video stream using an embedded,low-end GPU. We implement three pipelines to address this problem. The first is a detection-only feature-based method that finds objects with radial symmetry (suitable for circular EU-speed-limit signs). In this implementation, we leverage the graphics part of the GPU pipeline to perform the radial-symmetry voting step. The second is a template-based method that searches for image templates in the frequency domain using FFT correlations, suitable for both EU and US speed-limit signs. This method performs recognition (both detection and classification); it incorporates contrast-enhancement, composite filters, frequency-domain detection and classification, and temporal integration to aggregate results over many frames in its implementation. The third is classic GPU-based SIFT approach which provides a basis for evaluation of recognition results of the template-based approach. We show 88% detection accuracy using feature-based pipeline on an embedded system (Intel Atom CPU + NVIDIA GeForce 9200M GS GPU) running at 33 fps. In addition, we show 90% recognition accuracy using template-based pipeline on Intel Core2 Duo P8600 2.4GHz CPU and a NVIDIA GeForce 9600M GT GPU (a low-end GPU which can be used in embedded automotive system) running at 18 fps, superior in both accuracy and frame rate to the SIFT-based approach.
Pınar Muyan-Özçelik, Pınar Muyan-Özçelik, Jeffery M. Ota, and John D. Owens, “A Template-Based Approach for Real-Time Speed-Limit-Sign Recognition on an Embedded System using GPU Computing." In DAGM 2010: Proceedings of the 32nd Annual Symposium of the German Association for Pattern Recognition, volume 6376 of Lecture Notes in Computer Science, pages 162–171. Springer, September 2010.
Abstract We present a template-based pipeline that performs real-time speed-limit-sign recognition using an embedded system with a low-end GPU as the main processing element. Our pipeline operates in the frequency domain, and uses nonlinear composite filters and a contrast-enhancing preprocessing step to improve its accuracy. Running at interactive rates, our system achieves 90% accuracy over 120 EU speed-limit signs on 45 minutes of video footage, superior to the 75% accuracy of a non-real-time GPU-based SIFT pipeline.